The Psion SIBO Hardware Development Kit v1
I've been slowly going through the HDK, copying it out and reformatting it. The hope is to use it as a basis for building a new, updated HDK with more information than before.
This document is intended to provide guidance to anyone wishing to construct peripherals for the Psion SIBO (sixteen bit organiser) range of computers. It describes in detail all aspects of Psion peripheral hardware development and the structure of the software required to drive such peripherals.
It is the aim of this document to aid third party development engineers in producing production ready peripherals for any of the following Psion products: Series 3/3a, Workabout, HC and HCDOS. Mechanical and plastic moulding information and information on how to develop production test equipment is therefore also included. The emphasis throughout is on the two key Psion peripheral chips ASIC4 and ASIC5. Detailed information regarding their functionality is provided. The structure of Psion hardware device drivers is examined both in general outline and then with regard to two specific examples whose source code is provided in the appendix to this document. It has been assumed that the reader has some knowledge of a Psion computer such as the Series 3/3a and an understanding of how such a machine is programmed. A good understanding of electronics, the C programming language and 8086 assembler is also assumed.
Due to the continuous nature of development, information in this manual may change without notice. Developers are advised to contact Psion Support to confirm critical details prior to committing products to manufacture.
All present Psion computers are based around the proprietary SIBO architecture. A SIBO machine is
a battery-powered, 8086-based, computer system. SIBO stands for SIxteen Bit Organiser. The
architecture has been designed with the size, weight and power consumption of computers designed
for the portable environment in mind. The key components of the SIBO architecture are:
- An 8086 class processor.
- A sophisticated power management system that selectively powers subsystems under software control.
- A synchronous, high speed, serial protocol (the Psion SIBO serial interface) for communication between a machine and its peripherals.
- Solid State Disks (SSDs) that provide fast, low-power, silicon-based mass storage with no moving parts.
- Hardware protection of the system from aberrant software processes (trapping of out of range addressing and a watch-dog timer on interrupts being disabled).
- Real-time clock.
- ROM-resident system software.
- Graphics LCD display.
- A touch sensitive digitising pad that provides a pointing device (only available on some models).
- ISDN-8bit standard combo sound system (only available on some models).
The SIBO architecture has primarily been implemented in custom ICs called ASICs. At the time of writing there are ten different SIBO ASICs. Some of these ASICs have been designed for use inside peripherals and these will discussed in detail throughout this document. All SIBO ASICs have been implemented in surface mount packages and are based on a static CMOS technology. Current SIBO products in the MC, HC and Series 3 range are based on the same three principal chips. These are the V30H (an 8086-compatible processor) and two Psion custom chips known as ASIC1 and ASIC2. Later SIBO products including the Series 3a and Workabout have these three devices integrated into a single Psion custom chip known as ASIC9. The V30H is an enhanced 16-bit CMOS version of the 8088 found in the original IBM PC. It is software compatible with the 8088. The V30H is a fully static design which means that all the internal storage elements (i.e. its registers) are made from static rather than dynamic storage components. This in turn means that there is no minimum clock speed required to refresh the storage elements and the system clock can be stopped at any time with no loss of internal state. This technique is used extensively in the SIBO architecture to save power while the processor is idle (i.e. waiting for an event).
The Psion SIBO serial protocol is a proprietary synchronous two wire serial standard by which host Psion handhelds communicate with external devices. These devices will typically be Memory Packs (usually referred to as Solid State Disks or SSDs), RS232 and Centronics printer interfaces, fax modems, bar-code scanners, and so on. The SIBO architecture provides for two basic forms of expansion device, namely the extended internal expansion connection (as with SSDs) and the reduced external expansion connection (the 6-pin S3a serial port or the 11-pin LIF connector). The MC and HC range of computers have two SSD ports and two separate independent single row 25-way extended internal expansion ports. These ports have in addition to a Psion SIBO Channel, direct, parallel I/O from the processor. Direct connection to these machines 7.2 volt battery is included to support high power peripherals such as Printers and Barcode readers. The Series 3 range of computers have two ports for SSDs and a single, reduced, 6-pin expansion port, which provides only a Psion SIBO serial channel and limited power (<25mA). The Psion Workabout has two SSD ports, two internal expansion points, and one external expansion port. The single external expansion port uses an 11-pin Low Insertion Force (LIF) socket which provides a Psion SIBO channel, 25mA of current and additional lines required for detecting the presence of the Workabout cradle. Each internal expansion port consists of a single row 26-way connector carrying two high speed serial ports.
A range of Psion peripherals have been produced for connection to the Psion handhelds outlined above. These peripherals currently incorporate one of two custom integrated circuits (ASIC4 and ASIC5) that convert SIBO serial protocol signals to data bus TTL level voltages which enable memory and memory-mapped peripherals to be addressed. ASIC4 is used in SSDs and for memory-mapped peripherals. A typical ASIC4 peripheral for a Psion S3a would consist of an ASIC4 connected to port C of the host machine and a peripheral chip/device mapped into ASIC4's addressing space. ASIC5 is a general purpose I/O chip with a UART on board that can be run in several different modes. For example ASIC5 can be used for MCRs (magnetic card readers) or Centronics interfaces thereby simplifying peripheral design. Psion extended internal expansion ports carries an active low interrupt input line to the host controller circuitry. The reduced external expansion ports has an active high interrupt input line. The function of the interrupt can thus be programmed into the host machine's ASIC1 or ASIC9.
The low-level programming interface to a Psion handheld peripheral is encapsulated within an appropriate device driver. Psion device drivers are written in 8086 assembler and follow a prescribed pattern outlined later in this document. The construction of a peripheral and the coding of its complimentary device driver enable the developer to access its functionality through the means of library calls in a C program. Examples of such calls are
p_close(). I/O requests are routed through the device driver's strategy vector which maps to the PLIB
p_iow() call. The device driver is built using the Borland Turbo Assembler and resides in a single code segment. The device driver can be stored in either RAM or a ROM on board the peripheral or can be supplied on an SSD (solid state disk).
The Psion SIBO serial protocol
The Psion SIBO serial protocol is a general purpose method of bi-directional serial data transfer. It has been designed for synchronous communication between a host controlling device and a number of slave devices. On a hardware level, the SIBO serial protocol is implemented through Psion ASICs. The controlling device must contain an ASIC2 (or ASIC9) and the slave devices an ASIC4 or ASIC5. The various Psion ASICs are described in more detail below.
The synchronous SIBO serial protocol interface consists of 2 wires:
- CLK - A clock output from the controller to the slaves. Nominally 3.84 MHz.
- DATA - A bi-directional synchronous data line.
The data is transferred using a series of 12 bit frames including 8 data bits each. This equates to a theoretical maximum data transfer rate of approximately 312 Kbytes/second. Other bits of the frame contain control information. The "system" is generically defined by 2 protocol layers, namely the Physical layer and the Transport layer. These layers are described in detail in the next chapter.
Psion ASICs and what they do
ASIC stands for Application Specific Integrated Circuit and as previously indicated, these devices are widely used within Psion hardware. Summaries of the functionality of each ASIC that is relevant to peripheral development are presented below:
ASIC1 is the main system controller chip for the SIBO architecture. It connects directly to the 8086-based processor (i.e. the V30H) controlling all bus cycles to and from the processor. This configuration effectively forms a micro-controller like device that executes 8086 instruction codes. ASIC 1 is made up of a number of functional blocks including a bus controller, a programmable timer, an eight input interrupt controller, an LCD controller and the memory decoding circuitry.
ASIC2 is the peripheral controller chip for the SIBO architecture. It contains the system clock oscillator and controls switching between the standby and operating states. ASIC2 provides an interface to the power supply, keyboard, buzzer and SSDs. ASIC 2 includes the eight-channel SIBO serial protocol controller and provides interface circuitry to both the reduced external and extended internal peripheral expansion ports.
ASIC4 is a serial protocol slave IC for addressing memory and general memory-mapped peripherals. It is used in SSDs to convert SIBO serial protocol signals into addresses within the memory range of the memory pack. ASIC4 was designed to be a cut-down version of ASIC5 which was the original SIBO serial protocol slave chip.
ASIC5 is a general purpose I/O chip with a built-in UART that can be set to run in a number of different modes thereby simplifying the task of peripheral design. For example, it is possible to set up ASIC5 to run as a Centronics parallel port interface, an 8-bit parallel I/O port, a serial bar code controller or a serial RS232 converter.
ASIC9 is a composite chip comprising of a V30H processor, ASIC1, ASIC2 and general I/O and PSU control logic all on one IC. ASIC9 thus integrates all the digital logic required to produce a SIBO architecture computer less the memory onto one chip. ASIC9 has a few additional features such as an extra free-running clock (FRC) and a codec interface for sound.
Psion peripherals usually incorporate some circuitry to generate hardware interrupts. Both reduced external expansion ports (such as the LIF connector on the Workabout or the 6-pin serial port connector on the S3a) and extended internal expansion ports (such as the two single row 25-way HC connectors) carry an interrupt line. This is an active high input to the host machine's interrupt controller circuitry which resides on the logical equivalent of ASIC1. The OS intercepts all interrupts and can be requested to call a particular function within a controlling device driver. Eight hardware interrupts are supported by SIBO hardware. IRQ0 is the highest priority and IRQ7 the lowest. All interrupts are level triggered and must be serviced in the following order:
- Device asserts the appropriate interrupt request line.
- The interrupt controller unit within either ASIC2 or ASIC9 places onto the data bus the vector of the highest priority device with an interrupt pending. This enables the CPU to jump to the correct interrupt service routine code.
- During the interrupt service routine, the software clears the interrupt line by some action specific to the device.
- The interrupt service routine then informs the interrupt controller that the interrupt has been cleared by writing to the non-specific end of interrupt (NSEOI) location.
- If another interrupt is pending then go back to the second step.
With 8086-based processors, it is not possible to have nested interrupts.
The current range of Psion peripherals
There are currently a number of Psion peripherals in use and some of the key ones are outlined below in order to provide the developer with a feel for peripheral design issues:
Solid State Disks (or Memory Packs) use a built-in ASIC4 to decode SIBO serial protocol signals into memory addresses within the memory range of the SSD.
The HC Printer
The HC Printer translates SIBO serial protocol signals transmitted across the single row 25-way extended internal expansion socket of the host HC into a parallel 8-bit format that is compatible with the universal Centronics printer interface standard. The HC Printer unit contains an ASIC5 running in Centronics interface mode which acts as the serial protocol slave and requires a small number of support chips.
The 3-Fax contains an ASIC4 and a memory-mapped modem chip set which permits the host machine to transmit (but not receive) fax messages.
The Psion Barcode reader employs an ASIC5 running in serial mode to read the data received from the barcode decoder chip into a SIBO serial protocol format that can be transmitted to the host ASIC2/ASIC9.
Workabout RS232 Interface
This peripheral connects to the single row 26-way extended internal expansion port of the Workabout. It incorporates an ASIC5 running in its default mode to translate SIBO serial protocol signals into a TTL level (+/-5v) serial RS232 format using ASIC5's on-board UART. The TTL level RS232 signals are converted into the standard EIA format (+/-12v) before coming out on the conventional RS232 9-pin D-type connector.
The Psion SIBO Serial Protocol
The Psion SIBO serial protocol is a proprietary standard for bi-directional serial data transfer between a controlling device and a number of slave devices. The synchronous interface consists of 2 wires CLK and DATA as mentioned earlier:
- CLK - A clock output from the controller to the slaves. Nominally 3.84 Mhz for memory interfaces or 1.536.Mhz continuous for peripherals.
- DATA - A bi-directional synchronous data line.
The data is transferred using a series of 12 bit frames including 8 data bits each. This equates to a theoretical maximum data transfer rate of approximately 312 Kbytes/second. Other bits of the frame contain control information. The "system" is generically defined by 2 protocol layers:
- The Physical layer defining the hardware interface and frame structure.
- The Transport layer defines system control and register transfers between the controller and the slaves.
Using this system, a large number of higher level implementations can be defined. In normal use the controller will communicate to slaves in a point to point configuration. Multidrop configurations with a number of slaves attached to one channel of the controller are also supported.
As indicated in the previous chapter, the SIBO serial protocol controller circuitry resides in either an ASIC2 or an ASIC9 depending on the particular Psion hardware platform. The S3a and Workabout employ ASIC9 whereas the HC, MC and S3 use ASIC2.
As indicated above, the SIBO serial protocol consists of two lines that switch at 5V CMOS voltage levels:
This line is used to synchronously clock data between the controller and slaves. It is always output from the controller circuitry that resides in ASIC2/ASIC9. The clock should only be active during the transfer of data or when the serial channel is continuous clocking mode (used by ASIC5). At all other times it is tri-state pulled low.
Clock Timing Parameters
|Tckh||Width of clock high||65||130||-||nSec|
|Tckl||Width of clock low||130||130||-||nSec|
|Tcyc||Cycle time of clock||195||260||-||nSec|
This is a bi-directional line used to transfer data synchronously between the controller and slaves. The direction of the data line is not determined by the physical layer but by the control information in the transport layer. This is described in the next section. When no data transfers are in progress the data line is always set to input on both the controller and slaves. This line is pulled low. Data is changed on the falling edge of clock by the transmit device and latched into the receiving device on the rising edge of the clock.
The Physical Layer
This section specifies the low level protocol of the SIBO serial protocol. The physical layer protocol consists of a series of 12 bit frames. There are four types of frames:
- Null frames - Transmitted by controller to synchronise slaves.
- Control frames - Control information transmitted by controller to slaves.
- Data output frames - Data frame transmitted by controller to slaves.
- Data input frames - Data frame received by controller from a slave.
All 12 bit frames have the following structure:
|ST||Start bit. This bit goes high to indicate the start of a valid frame.|
|CTL||Control bit. When low indicates this is a control frame. High indicates a data frame.|
|I1||Idle bit. Used to turn around direction of data line. Normally Low.|
|I2||Idle bit. Used to turn around direction of data line. Normally Low.|
This is a special frame transmitted by the controller to ensure all slaves are synchronised. It is generated by transmitting 12 clock pulses with the data line set to input. Since the data line is pulled low this results in 12 zeroes being transmitted.
This frame is transmitted from the controller to one or more slaves. The data line is an output from the controller throughout the whole frame. The bits in the frame have the following value in a control frame:
|ST Start Bit||This bit goes high to indicate the start of a valid frame.|
|CTL Control Bit||Low to indicate this is a control frame.|
|I1 Idle Bit||Set low.|
|D0-D7 Data Bits||8 bits of control information.|
|I2 Idle Bit||Set low.|
Data Output Frame
This frame is transmitted from the controller to one or more slaves. The data line is an output from the controller throughout the whole frame. The bits in the frame have the following value in a data output frame:
|ST Start Bit||This bit goes high to indicate the start of a valid frame.|
|CTL Control Bit||High to indicate this is a data frame.|
|I1 Idle Bit||Set low.|
|D0-D7 Data Bits||8 bits of control information.|
|I2 Idle Bit||Set low.|
Data Input Frame
This frame is received by the controller from a slave. The data line is an output from the controller for cycles 1 and 2 and input to the controller for cycles 4 to 11. The bits in the frame have the following value in a data input frame:
|ST Start Bit||
Output from controller. This bit goes high to indicate the start of a valid frame.
|CTL Control Bit||
Output from controller. High to indicate this is a data frame.
|I1 Idle Bit||
Used to turn around direction of data line. Both controller and slave should tri-state the data line during this bit. This bit should be low due to pull down resistor on data line. The controller changes the data line from output to input at the end of cycle 2. The slave changes the data line from input to output at the start of cycle 4.
|D0-D7 Data Bits||
Output from slave 8 bits of data transmitted by slave. Controller sets data
|I2 Idle Bit||
Used to turn around direction of data line. Both controller and slave should tri-state the data line during this bit. This bit should be low due to pull down resistor on data line. The slave changes the data line from output to input at the end of cycle 11.
Data Line Direction
The following table summarises the direction of the data line.
|Data output from controller:|
- T Tri-state
- I Input
- O Output
The Transport layer
This section specifies the transport level protocol that operates above the SIBO serial communication physical layer. The transport layer protocol controls the serial communication between the SIBO Protocol Controller (SPC) and a number of SIBO Protocol Slave (SPS) devices. The following rules apply:
- The interface is controlled by the writing of control bytes from the controller to the slaves. Control bytes cannot be written by the slaves. Unsolicited data cannot be sent from the slave to the controller.
- The controlling device contains two registers to communicate to the slaves. These are the control register (byte, write only) and the Data register (byte or word, read/write). Control bytes are transmitted to the slaves by writing to the control register.
The format of the control byte is as follows:
The control word can have 2 distinct formats depending on the setting of bit 7 the Select (S) bit:-
|0||This is the slave select mode. This mode is for selecting, deselecting and resetting slaves.|
|1||This is the slave control mode. This mode is for communicating with a slave which has been previously selected using the select slave command.|
Slave select mode
The format of the slave select byte is as follows:-
- R single reset bit.
- IIIIII 6 bit ID field.
The 6 bit ID field is a property only of the slave. No slave may have an ID of zero, hence there can be 63 different slaves connected to one controller. The reset bit (R) controls whether the slave(s) are selected or reset. If R = 0 slave(s) are reset, R = 1 slave(s) are selected. Slave select control bytes can be summarised by the following table:-
|0||0||0||Reset all slaves|
|0||0||xx<>0||Reset specific slave with ID = xx|
|0||1||0||Deselect slave (does not reset slave)|
|0||1||xx<>0||Select slave with ID=xx and read slave info (see below).|
The Reset function is dependant on the slave. It would normally put the slave into a known passive reset state.
Select Slave with ID=xx (S=0,R=1)
This is a special command that causes a slave with ID=xx to transmit to the controller an 8 bit information field. This field depends entirely on the slave but must be non zero. A reply of 0 indicates that there is no slave of the requested ID present.
Slave control mode
This mode is for communicating with a slave which has been previously selected using the select slave command described above. The format of the control word in slave select mode is as follows:-
- R/W Read/write select. 0 = write, 1 = read
- B/W Data transfer size. 0 = 1 byte transfer, 1 = word (2 byte transfer).
- S/M Single/Multi transfer mode. 0 = single, 1 = multibyte.
- XXXX = 4 bits of data to slave.
Note the meaning of the 4 bits of data (XXXX) is entirely dependent on the slave. The settings of R/W,B/W,S/M bits in the control word determine the size, type and direction of subsequent data transfers in the following manner:-
|0||0||0||Write a single byte to slave|
|0||0||1||Write a number of single bytes to slave|
|0||1||0||Write a byte pair to slave (not implemented)|
|0||1||1||Write a number of byte pairs to slave (not implemented)|
|1||0||0||Read a single byte from slave|
|1||0||1||Read a number of single bytes from slave|
|1||1||0||Read a byte pair from slave (not implemented)|
|1||1||1||Read a number of byte pairs from slave (not implemented)|
Write a single byte
This command readies the currently selected slave to receive a byte of data and sets up the controller so that the next byte (or the LSB of a word) written to its data register will be transmitted to that slave. Anything further written to the controller's data register will have no effect.
Write a number of single bytes
This command readies the currently selected slave to receive a number of sequential bytes of data. The slave will expect to receive data bytes until another control byte is received. The controller is set up so that the next byte (or the LSB of a word) written to its data register will be transmitted to that slave. All subsequent bytes written to the controller's data register will be transmitted to the slave. This will continue until another byte is written to the controller's control register.
Write a byte pair
This command readies the currently selected slave to receive two bytes of data and sets up the controller so that the next word written to its data register will be transmitted to that slave (LSB first). Anything further written to the controller's data register will have no effect.
Write a number of byte pairs
This command readies the currently selected slave to receive a number of sequential byte pairs of data. The slave will expect to receive byte pairs until another control byte is received. The controller is set up so that the next word written to its data register will be transmitted to that slave (LSB first). All subsequent words written to the controller's data register will be transmitted to the slave. This will continue until another byte is written to the controller's control register.
Read a single byte
This command triggers a byte to be transmitted from the selected slave to the controller. This byte can then be read from the LSB of the controller's data register. Further reads of the controller's data register will return the same data but have no effect on the protocol.
Read a number of single bytes
This command triggers a byte to be transmitted from the selected slave to the controller. This byte can then be read from the LSB of the data register. This read will trigger the next byte to be transmitted to the data register of the controller. All subsequent reads of the controller's data register will trigger further bytes to be transmitted to the controller. This will continue until another byte is written to the controller's control register.
Read a byte pair
This command triggers a byte pair to be transmitted from the selected slave to the controller. This word can then be read from the controller's data register. Further reads of the controller's data register will return the same data but have no effect on the protocol.
Read a number of byte pairs
This command triggers a byte pair to be transmitted from the selected slave to the controller. This word can then be read from the controller's data register. This read will trigger the next byte pair to be transmitted to the data register of the controller. All subsequent reads of the controller's data register will trigger further byte pairs to be transmitted to the controller. This will continue until another byte is written to the controller's control register.
The time taken for commands to be processed and data sent is shown below. The time is given in SIBO pack protocol clock cycles. The length of a clock cycle is nominally 260 nanoseconds for a clock frequency of 3.84 MHz.
|Receive and process the control byte||12 cycles|
|Byte transfer to or from slave||12 cycles|
|Byte pair transfer to or from slave||24 cycles|
When writing to the controller's data and control registers the following rules apply:
- After writing to the control register there must be a delay of at least 12 cycles before the data register is accessed or another control word is written.
- To read a word from the data register after the command to read byte pair is issued there must a delay of at least 12 (for control byte)+24 (for the byte pair transfer)= 36 cycles.
- To perform a multiple byte pair write there must be a delay of at least 12 cycles after the command is written to the control register before the first word can be written to the data register and a delay of at least 24 cycles between subsequent writes to the data register.
A slave can be in one of 5 states. Note a control byte can be received and interpreted at any time.
- Waiting to receive a data byte or control byte
- Waiting to receive a data byte pair or control byte
- Waiting to transmit a data byte or control byte
- Waiting to transmit a data byte pair or control byte
- Waiting to receive control byte only
This section will contain information regarding mechanical and plastic moulding for Series 3/3a, Workabout and HC machines that is deemed to be of especial importance to developers who are considering producing peripherals for these particular Psion platforms.
The Psion Series 3/3a range
S3a/Series 3 Reduced External Expansion Port
The Psion Series 3/S3a personal digital assistants have two SSD slots and provide access to external peripheral units through a single reduced internal expansion port, port C, on the left edge of the machine. The reduced external serial interface expansion port from the Series 3/3a forms six wires. The purpose of each is described in the table below. In addition to data, clock and power an active high interrupt line is provided. This allows the peripheral device to generate an interrupt within the host series 3/3a. The level of interrupt that is generated depends on both the machine and the expansion port that is used. Either ASIC4 or ASIC5 can act as the other end of the Psion Serial Interface. With exception of the interrupt line all used signals should be connected directly to the appropriate pins on ASIC4/5.
|1||MSD||Data line||ASIC4/5 SDAT|
|2||MCLK||Serial clock||ASIC4/5 SCLK|
|3||Vcc||+5 volt supply||Vcc|
|5||SSD/INT||Interrupt Line||Interrupt source/GND|
|6||SCK/EXON||Not used in this scenario||Do not connect|
MSD and MCLK form a single master SIBO serial protocol channel. This is normally channel 7 on a Series 3 and channel 5 on an S3a. The serial channel clock can be continuously enabled to provide a free running clock for expansion devices. The frequency is fixed at 1.536MHz regardless of the system clock frequency. SDKs/INT and SCK/EXON are both dual function pins. SDKS and SCK form a single slave SIBO serial protocol channel. This can be combined with MSD and MCLK to form a bi-directional high speed data link. SDS/INT can also be used to as an active high interrupt input. The function of SDS/INT can be programmed in ASIC2 or ASIC9. A rising edge on the SCK/EXON input will bring the system out of the standby state into the operating state. VCC is a +5 volt supply that is switched off when the system is in the standby state and is switched on when the system is in the operating or idle state. The maximum current that can be drawn is 25mA. Opening the pack doors on either an S3a or a Workabout will cut power to external peripherals.
The reduced expansion port is made up of a 6-way two row connector spaced on a 2x3 way 0.1 inch pitch. The diagram below shows the physical connector numbering:
The male plug is connected to a 0.5m long plastic moulded 3-link cable assembly (part no. 25020013) which is terminated in a six-pin in-line connector which connects to a 6-way 1.5mm pitch transition header (part no. 47000106).
The Psion Workabout
The Workabout Expansion Interfaces
The Psion Workabout provides a rugged and easy-to-use computer system for a wide range of mobile corporate needs. The machine can be readily adapted to support various peripheral units such as barcode scanners and modems attached to the expansion ports. The Workabout has a 26-way extended internal expansion interface and a special 11-pin reduced external expansion interface.
Workabout Extended Internal Expansion Interface
The pin-out of the Workabout 26-way internal Torson connector is outlined below:
|Torson 26 way connector pin||Workabout Signal name|
|2||NICD (not used)|
|4||Vh (not used)|
|7||CODEN (not used)|
|8||AMPEN (not used)|
|9||VOL0 (not used)|
|10||VOL1 (not used)|
|11||SCK (not used)|
|12||SYNC (not used)|
|13||SYNC (not used)|
|14||SIN (not used)|
|15||SOUT (not used)|
|16||ESDOE (not used)|
|19||EINT1 (active low)|
|22||EINT2 (active low)|
|23||THM (not used)|
- Vcc1 is 3.0V nominal power supply. Current available from Workabout is limited to 100mA.
- Vcc2 is 5V nominal power supply. Current available from Workabout is limited to 200mA.
- RUN is low when powered down and high when powered up. It is used to power down or reset the peripheral module.
- SCK2 and SCK3 are serial data clocks. The clocks are left running continuously at 1.536MHz when the serial port is in use. They are used to clock the UART in ASIC5 in the RS232 AT/TTL and AT/Barcode modules respectively.
- SD2 and SD3 are bi-directional serial data lines used in the RS232 AT/TTL and AT/Barcode modules respectively.
- EINT1 and EINT2 are active low signals for interrupt input.
- EXON is an active high signal used to turn on the Workabout.
- All of the above logic signals are at 3.0V or 3.3V levels, depending upon the logic supply Vcc1.
- Lines currently described as unused relate to a yet unspecified codec interface.
Workabout Reduced External Expansion Interface
For the Workabout reduced external expansion interface, a new 11-pin Low Insertion Force (LIF) connector has been designed for connecting the computer to the Cradle System. The computer mounted male LIF may be weather proofed, the cable mounted female LIF cannot. Currently the LIF connector cover can be moulded with a polarising pin in one of two positions. The facility exists to manufacture the cover with the polarising pin in two more positions, giving four possible variants. If more than four versions are required it is possible to have the cover and the socket bezel moulded in a range of colours to differentiate between variants. The polarising options are presented below:
Pin Definition for LIF - PFS Connector
More to come...