ASIC stands for Application Specific Integrated Circuit. These devices are widely used within Psion hardware. Some are well documented, others barely mentioned in anything but internal documentation. This is a list of ASICs specific to the SIBO range.
ASIC1 is the main system controller chip for the SIBO architecture. It connects directly to the 8086-based processor (i.e. the V30H) controlling all bus cycles to and from the processor. This configuration effectively forms a micro-controller like device that executes 8086 instruction codes. ASIC1 is made up of a number of functional blocks including a bus controller, a programmable timer, an eight input interrupt controller, an LCD controller and the memory decoding circuitry.
ASIC2 is the peripheral controller chip for the SIBO architecture. It contains the system clock oscillator and controls switching between the standby and operating states. ASIC2 provides an interface to the power supply, keyboard, buzzer and SSDs. ASIC2 includes the eight-channel SIBO Serial Protocol controller and provides interface circuitry to both the reduced external and extended internal peripheral expansion ports.
Power IC, specific to the MC range. Used for charging NiCd power packs.
ASIC4 is a serial protocol slave IC for addressing memory and general memory-mapped peripherals. It is used in SSDs to convert SIBO serial protocol signals into addresses within the memory range of the memory pack. ASIC4 was designed to be a cut-down version of ASIC5 which was the original SIBO serial protocol slave chip.
ASIC5 is a general purpose I/O chip with a built-in UART that can be set to run in a number of different modes thereby simplifying the task of peripheral design. For example, it is possible to set up ASIC5 to run as a Centronics parallel port interface, an 8-bit parallel I/O port, a serial bar code controller or a serial RS232 converter.
The first of the three publicly-undocumented ASICs.
Known internally as 'the voice ASIC,' ASIC6 is the support chip for use with the TMS320C10 DSP. It is primarily controlled via an MC serial channel with minor control from the DSP. The ASIC contains an extremely limited version of an ASIC5 in Pack mode, allowing access to the on board ROM and RAM by the MC. The DSP is unable to access the ROM, the RAM is the main system memory. Access to the RAM by the MC is non-standard as it is arranged in words of two bytes. There is a second serial interface for talking to the combo, the SLD bus.
The second publicly-undocumented ASIC. Additional glue logic for the MC range.
The final publicly-undocumented ASIC. So far we have very little information about ASIC8, but we believe that it was meant to be a peripheral chip combining features from ASIC4 and ASIC5.
ASIC9 is a composite chip comprising of a V30H processor, ASIC1, ASIC2 and general I/O and PSU control logic all on one IC. ASIC9 thus integrates all the digital logic required to produce a SIBO architecture computer less the memory onto one chip. ASIC9 has a few additional features such as an extra free-running clock (FRC) and a codec interface for sound.